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  • This course gives deeper understanding of the Xilinx FPGA Design & Timing closure flow.
  • The course focuses on the subtleties of the Xilinx ISE flow and its add-on tools such as the PlanAhead, FPGA Editor and Constraints Editor. By mastering the tools and the design methodologies presented in this course, participants will be able to close the timing of their designs faster, and also shorten the development time, and lower development costs. This course combines insightful lectures with practical lab exercises to reinforce key concepts.

Course Content

Module1 : Timing Constraints
  • Clock constraints
  • Path Specific constraints
  • False path constraints
  • Input / Output path constraints
  • Specifying Clock regions
  • Viewing and Analyzing Timing Reports using Timing Analyzer

Module2 : Advanced Synthesis & Implementation flow

  • Synthesis Options
  • Translate Options
  • MAP Options
  • PAR Options
  • BitGen Options

Module3 : Advanced FPGA Timing closure flow

  • Typical FPGA Timing closure flow
    • RTL coding Techniques
    • XCF Constraints
    • Effective Floorplanning
    • Editing UCF Constraints

Module4 : Advanced FPGA Implementation for higher performance

  • Hierarchical Synthesis
  • Relationally Placed Macros
  • Optimizing critical path using FPGA Editor
  • Re-entrant Routing

Module5 : Mini Project

  • Standard mini projects will be exercised